From 02566303d8b438b995cfb4ef0d0116c04781332a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?King=20K=C3=A9vin?= Date: Mon, 27 Jun 2022 14:05:42 +0200 Subject: [PATCH] doc: put development instructions in seperate file --- DEVELOPMENT.md | 84 +++++++++++++++++++++++++++++++++++++++++++++++ README.md | 88 +------------------------------------------------- 2 files changed, 85 insertions(+), 87 deletions(-) create mode 100644 DEVELOPMENT.md diff --git a/DEVELOPMENT.md b/DEVELOPMENT.md new file mode 100644 index 0000000..de95f04 --- /dev/null +++ b/DEVELOPMENT.md @@ -0,0 +1,84 @@ +requirements +============ + +to be able to generate the outputs you need following software: +- rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files) +- [QEDA](http://qeda.org/): to generate footprints for the parts +- [Lepton EDA](https://github.com/lepton-eda/lepton-eda): for the schematic capture +- [pcb-rnd](http://repo.hu/projects/pcb-rnd/): for the board layout +the output generation is automatized. + +schematic +========= + +library +------- + +almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software. +the `library` folder contains the QEDA parts definitions. + +to install QEDA using NPM from the official repository: +~~~ +sudo npm install -g qeda +~~~ + +to install QEDA from the sources: +~~~ +git clone https://github.com/qeda/qeda +cd qeda +npm install +sudo npm install --global +~~~ + +to generate the parts: +~~~ +rake library +~~~ + +this will use the parts definition (.yaml files) in the `library` to generate [gEDA gschem](http://wiki.geda-project.org/geda:gaf)/[Lepton EDA](https://github.com/lepton-eda/lepton-eda) symbols (.sym files) in the `geda/symbols` folder, and [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/) footprints (.lht files) in the `coraleda/subc` folder. + +only the QEDA parts in subfolders within `library` come from the [QEDA library](https://doc.qeda.org/library/), but the files are included in this project for simplicity and archiving purposes. +all other parts are custom and written for this project. + +schematic +--------- + +the `.sch` file is the schematic source file. +it has been drawn using [Lepton EDA](https://github.com/lepton-eda/lepton-eda). + +it uses standard symbols, and the ones in the `geda/symbols/` folder. +most symbols are generated by QEDA as described above. + +to export the netlist (in tEDAx format): +~~~ +rake netlist +~~~ + +to export as pdf: +~~~ +rake print +~~~ + +BOM +--- + +to export the bill of material (as CSV): +~~~ +rake bom +~~~ + +board +===== + +the `.lht` file is the board layout source file. +it has been drawn using [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/). + +it uses the symbols from the `coraleda/subc/` folder. +most symbols are generated by QEDA as described above. +`oshw_logo.lht` is just the Open Source Hardware Logo. +it been generated from https://oshwlogo.cuvoodoo.info/. + +to export gerber files for PCB manufacturer (and photo preview + overview document): +~~~ +rake fabrication +~~~ diff --git a/README.md b/README.md index c90ddbc..800b078 100644 --- a/README.md +++ b/README.md @@ -37,7 +37,7 @@ only populate it to debug the board. the READY LED will we on when the BUGGED LED isn't. this allows to always check if the battery is empty, but this also drains the battery even when not testing because an LED is always on. -the first prototype of the board (v0.3) offer three populating options, depending on the available NOR gate part: +the first prototype of the board (v0) offers three populating options, depending on the available NOR gate part: - 1x SOIC-14 package: U1+C1 - 2x SOT23-5 pachgae: U2+C2, U3+C3 @@ -68,89 +68,3 @@ the TEST circuit simulates an integrated circuit by putting a 100 nF capacitor a because of the 1 k Ohm inline resistor, and limited 3.3 V provided by the battery, a maximum of 3.3 mA can be drawn by the USB plug. this is often not enough to power up integrated circuit properly, particularly if they use a radio interface. thus it is safe to use the USB bug detector on bugs, without activating it. - -requirements -============ - -to be able to generate the outputs you need following software: -- rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files) -- [QEDA](http://qeda.org/): to generate footprints for the parts -- [Lepton EDA](https://github.com/lepton-eda/lepton-eda): for the schematic capture -- [pcb-rnd](http://repo.hu/projects/pcb-rnd/): for the board layout -the output generation is automatized. - -schematic -========= - -library -------- - -almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software. -the `library` folder contains the QEDA parts definitions. - -to install QEDA using NPM from the official repository: -~~~ -sudo npm install -g qeda -~~~ - -to install QEDA from the sources: -~~~ -git clone https://github.com/qeda/qeda -cd qeda -npm install -sudo npm install --global -~~~ - -to generate the parts: -~~~ -rake library -~~~ - -this will use the parts definition (.yaml files) in the `library` to generate [gEDA gschem](http://wiki.geda-project.org/geda:gaf)/[Lepton EDA](https://github.com/lepton-eda/lepton-eda) symbols (.sym files) in the `geda/symbols` folder, and [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/) footprints (.lht files) in the `coraleda/subc` folder. - -only the QEDA parts in subfolders within `library` come from the [QEDA library](https://doc.qeda.org/library/), but the files are included in this project for simplicity and archiving purposes. -all other parts are custom and written for this project. - -schematic ---------- - -the `.sch` file is the schematic source file. -it has been drawn using [Lepton EDA](https://github.com/lepton-eda/lepton-eda). - -it uses standard symbols, and the ones in the `geda/symbols/` folder. -most symbols are generated by QEDA as described above. - -to export the netlist (in tEDAx format): -~~~ -rake netlist -~~~ - -to export as pdf: -~~~ -rake print -~~~ - -BOM ---- - -to export the bill of material (as CSV): -~~~ -rake bom -~~~ - -board -===== - -the `.lht` file is the board layout source file. -it has been drawn using [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/). - -it uses the symbols from the `coraleda/subc/` folder. -most symbols are generated by QEDA as described above. -`oshw_logo.lht` is just the Open Source Hardware Logo. -it been generated from https://oshwlogo.cuvoodoo.info/. - -to export gerber files for PCB manufacturer (and photo preview + overview document): -~~~ -rake fabrication -~~~ -